1. Field of Invention
The present invention relates to a method of fabricating a DRAM capacitor. More particularly the present invention relates to a method for forming a bottom electrode of the capacitor.
2. Description of Related Art
The memory function of a Dynamic Random Access Memory (DRAM) is controlled via a voltage of a bit line provided on the source region of a Metal Oxide Semiconductor (MOS) transistor. This allows the movement of the internal charges of the capacitor to read and write data. In such a case the internal charges of capacitor are in a non-equilibrium state. Since it is easy to lose charges and to produce leakage current in the non-equilibrium state. It is necessary to refresh the capacitor with a certain frequency to compensate for the charge loss in a timely manner, in order to prevent read/write signal errors caused by current loss in the capacitor.
Conventionially the frequency for refreshing a normal capacitor depends on the number of charges that can be stored in the capacitor. The more charges that the capacitor can store, the smaller is the influence by the noise signal in the read/write signal transmission. Meanwhile, the frequency for refreshing can also be lowered to improve the DRAM read/write speed. Thus, the capability to increase the charge storage in the capacitor has become a development trend.
In addition to an improvement in the conducting material and dielectric layer of the capacitor, an increase in the surface area of the capacitor also allows greater charge storage in the capacitor. The design of the well known bottom electrode of capacitor having a cylinder structure has been developed to increase the surface area of the capacitor. By forming a hollow in the conductive layer the surface area of the bottom electrode of capacitor is increased. The surface area of the sidewall of the hollow is the increased surface area of the bottom electrode of capacitor. To increase the surface area of the bottom electrode of capacitor more effectively, it is necessary to have a greater thickness for forming the conductive layer of the bottom electrode of capacitor. Since the conductive layer is conventionally formed by deposition, it takes quite a long time to deposit thicker conductive layer. This slows down the whole process of the capacitor. Additionally, due to the greater thickness of the conductive layer, cylinder structures of the bottom electrode of the capacitor are slimmer structures after hollows are formed. These slimmer structures are easily broken in the subsequent processes, influencing the quality of the capacitor. Thus, this leads to a reduction in yield.
FIG. 1 is a cross-sectional diagram showing a bottom electrode structure for a capacitor having a cylinder structure fabricated according to the prior art.
Referring to FIG. 1, there are a dielectric layer 102 on a substrate 100, and a contact opening 104 in the dielectric layer 102. A conductive layer fills the contact opening 104 and covers the dielectric layer 102. There are hollows 108 in the conductive layer 106, so that the conductive layer 106 is showing the cylinder structure. Since the thickness of the conductive layer 106 is relative to the surface area of bottom electrode, the thicker the conductive layer 106, the more the surface area of the bottom electrode is increased by the cylinder structure. In order to yield a larger surface area of the bottom electrode, the conductive layer 106 is often very thick, and may be as thick as about 800 .ANG.. As a result it takes a long time to form the conductive layer 106 by deposition. This lengthens the capacitor process time, which reduces production efficiency.
Furthermore, when the thickness of the conductive layer 106 reaches a certain extent and after the hollow 108 is formed in the conductive layer 106 the cylinder structure of the conductive layer 106 is quite slim. The slim cylinder structure is easily broken by stress in the subsequent processes. This results a poor quality capacitor, leading to a yield reduction.